1. Field of the Invention
The present invention relates to a semiconductor device having an MOS (metal-oxide semiconductor) construction, particularly a device called a flash memory, and a method of the production thereof.
As a non-volatile storage, for example, an EPROM (erasable programmable read only memory) is known in which stored data can be erased by irradiation of ultraviolet rays. Since an EPROM requires a step for the irradiation of ultraviolet rays and costs of the rewriting of data, an EEPROM (electrically erasable programmable read only memory) has recently been employed as a non-volatile storage capable of electrically rewriting data. Among various types of EEPROM, a flash memory capable of collectively erasing data in units of words or chips has particularly been considered as a non-volatile storage substituting for magnetic storage mediums such as floppy disks.
2. Description of the Related Art
Generally speaking, there are two types of flash memory; one is a NAND-type flash memory, and the other a NOR-type flash memory. For the production of flash memories, some methods are known in the art.
In one typical method of producing a NOR-type flash memory, an oxidized film prepared on a silicon wafer surface is patterned to form a given field oxidation film, and at least two gate electrodes provided with floating and control gate electrodes and an impurity diffused region between the gate electrodes for a common source electrode are then formed. In this method, a photolithography process is used for the formation of the field oxidation films, in which a resist pattern is transferred to the underlying oxidized film. A photolithography process is also used for fabricating the gate electrodes. Owing to the difficulty in the precise transfer of a fine resist pattern by photolithography, the pattern transfer is not always fully effected (particularly, the corners of each of the formed field oxidation films are often rounded), and in the case of a deviated mask alignment when making the gate electrodes, the relation between the locations of the gate electrodes and the field oxidation films is deviated from the intended state, and consequently, variability of characteristics of the memory cells can be caused. The higher the integration in a flash memory, the graver these problems.
There is another method of manufacturing a flash memory, in which gate electrodes are formed on a gate oxidation film and field oxidation films, and the gate oxidation film and the field oxidation films are then patterned between the gate electrodes in order to make an impurity diffused region for a common source electrode between the gate electrodes. In the process of the formation of the impurity diffused region, a resist film is patterned so as to cover the gate electrodes and a region not to be etched, and the exposed oxide films are then anisotropically etched by, e.g., reactive ion etching. To fully cover the gate electrodes, a margin for mask alignment is required between each of the gate electrodes and the region to be etched, i.e., the gate electrodes inevitably have a resist material having a certain width in the side toward the region to be etched between the electrodes. The need for the space for the mask alignment margin is disadvantageous for the high integration in a flash memory.
Thus, known methods of making a flash memory use a photolithography process to form an impurity diffused region for a common source electrode. In addition, no method is known in which an impurity diffused region in a flash memory is self-alignedly formed. To provide a method, which allows a highly integrated flash memory to be created in a self-aligned manner, would therefore be beneficial in the art.
In the production of semiconductor devices other than a flash memory, it is known to use a side wall formed immediately adjacent to the side of a gate electrode, as a mask to effect the etching of a substrate and the ion implantation thereinto.
For example, JP 3-46275(A) discloses a method of making a semiconductor device, in which spacers (i.e., side walls) are formed on both sides of a gate electrode, the spacers are then used, as masks, to etch a semiconductor substrate on which the gate electrode and the spacers have been formed, and to then implant an impurity ion into the etched regions of the substrate. The ion-implanted regions are allocated to source and drain regions in a transistor.
JP 2-72671(A) discloses a method of manufacturing a non-volatile memory device such as an EPROM. The method makes it possible to make a non-volatile memory device in which both source and drain regions of transistor of the memory cell thereof are each made up of regions having a high density and a low density of impurity. According to the disclosure of the document, layers of an insulation film, a floating gate electrode, another insulation film, and a control gate electrode are formed in sequence on a semiconductor device; a control gate electrode is then preferentially formed; an impurity ion is implanted into the regions of semiconductor in both sides of the formed control gate electrode using it as a mask; side walls are formed on both sides of the control gate electrode, and then used to pattern the underlying floating gate electrode; and subsequently, the control gate electrode and side walls are used as a mask for a further ion implantation.
To the applicant's knowledge, no methods are known in which the production of a highly integrated flash memory is effected using a side wall immediately adjacent to a side of a gate electrode to self-alignedly form an impurity diffused region to be used as a common source electrode.